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Supercomputing goes back to school

Between talks, researchers socialize with their colleagues and discuss their use of emerging technologies. Image courtesy TACC.

When it comes to parallel programming and other facets of high-performance computing (HPC), the Texas Advanced Computing Center (TACC) in Austin, US, offers more than 50 training sessions each year. TACC's experts in hardware, software, visualization, and data-driven science guide computational scientists-in-training in hands-on classes as well as Virtual Workshops. (Workshops range from a few hours to the weeklong Summer Supercomputing Institute.) They also teach required courses for The University of Texas at Austin (UT Austin) certificate in Statistics and Scientific Computing.

"We teach our users everything they need to know to quickly get started on the system, and to effectively and efficiently use it in the support of their research projects," says Chris Hempel, director of user services at TACC. "Training the user community to use HPC resources is a contributing factor to the success of TACC."

Stampede incorporates a new processing architecture — the Intel Xeon Phi many integrated core (MIC) coprocessor — that is novel even for experienced supercomputer users. The Xeon Phi is programmed using the same computer languages as traditional CPUs, but has some key differences that require basic instruction and an understanding of the new paradigm.

Eric Fahrenthold, a long-time supercomputing user and mechanical engineering professor at UT Austin, attended a Stampede workshop on the MIC architecture last spring. Attending the session provided an on-ramp for using the MIC – he didn't have to teach himself how to use it by searching the web or combing through white papers.

"TACC explained the architecture and showed me how to test my code's performance when using the MIC," he says. "I found out very quickly what the code performance issues are, and the various ways in which I can access coprocessor cores."

“Even though I have a lot of experience with HPC, learning about the MIC system’s hardware and software was new,” he says. “I like to take advantage of TACC consulting and tutorials because they allow me to concentrate on modeling the physics – when I need to understand system architecture and system software issues, I rely on TACC support.”

Scenes from the 2013 Summer Supercomputing Institute, where researchers learned how to utilize TACC's advanced resources, including the Stampede supercomputer. Image courtesy TACC.

The Parallel Computing on Stampede workshop is intended for beginner and intermediate HPC users – and anyone interested in using Stampede in the future. The two-day session is offered in-person and via webcast to accommodate users across the country. The training is free to UT Austin, The University of Texas System, TACC partners, and Texas higher education research communities, as well as to participants in the National Science Foundation-funded XSEDE (Extreme Science and Engineering Discovery Environment) project.

It’s been a whirlwind tour for many of the Stampede experts at TACC. They began offering Stampede training in November 2012 with a special session at the SC12 conference in Salt Lake City, US – but TACC staff are not the only ones participating in the effort. The Cornell University Center for Advanced Computing (CAC), in Ithaca, New York, US – an academic partner in the Stampede project – began offering training for local and regional researchers, as well as remote participants, in fall 2012.

Cornell specializes in the development and dissemination of training materials, and offers up to 64 hours of Stampede-specific training annually to reach hundreds of researchers in a variety of fields. “Biology, applied math, nutritional sciences, civil engineering, earth and atmospheric science, mechanical engineering, pharmacology — our attendees are very diverse,” says Susan Mehringer, assistant director of the Cornell University CAC, who leads their training effort.

The training is designed to provide a practical introduction to Stampede and the new Intel Xeon Phi architecture. Staff offer lectures and hands-on exercises to acquaint researchers with the new platform and different execution modes. The training also covers parallelization and optimization through example testing and reports. Researchers are also invited to bring their own codes to compile for the Xeon Phi.

To learn about future workshops at TACC, Cornell, and elsewhere, visit the TACC training page.

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