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iSGTW Feature - Keeping up with Moore's Law


Feature - Keeping up with Moores Law

The NanoWire user interface.
Image courtesy of nanoHUB

Silicon nanowire transistors are promising devices for future integrated circuits.

Researchers in this field are interested in geometries and properties of materials that vary on an atomic length scale; they study quantum states and the relationship between voltages and currents at these scales.  

But not all nano-device engineers are nuts for computers. Many prefer to let other people worry about the computational end of things. Since this research depends heavily on simulations of nano-device behavior under varying conditions, the door is wide open for the development of accessible and intuitive computational tools.

Enter Gerhard Klimeck of Purdue University, technical director of the National Science Foundation Network for Computational Nanotechnology. Klimeck and his colleagues have developed the user-friendly NanoWire computational tool, accessible via the web-based nanoHUB.  

On nanoHUB, researchers set up a NanoWire simulation through a graphical interface that allows input of device parameters, ranges of voltages to test, and so forth.

A simple click on “Simulate” transparently sends a set of parallel processes off to Open Science Grid, TeraGrid and/or the local cluster at Purdue. The computers send back complex and enticing electrostatic potentials and quantum eigenstates. NanoWire makes the results easy to interpret, and the researchers are on their way to optimizing transistor designs.

Following Moore’s Law: The number of transistors on a chip doubles about every two years.
Image courtesy of University of Cincinnati

“Users are interested in ease of use, not Unix commands. They need to be able to set up their experiment, explore their data interactively and ask ‘what if’ questions,” says Klimeck.

Enter Saumitra Mehrotra and Kenneth Roenker of the University of Cincinnati, Ohio. According to them, one of the leading challenges in producing nanoscale circuits is the variation in device performance due to inherent variability in the fabrication process.

Mehrotra and Roenker studied the effects on silicon nanowire MOSFET voltage characteristics of varying body thickness, gate length and gate dielectric thickness.

“We ran over 500 simulations on NanoWire and gained an insight into how superior the silicon nanowire MOSFET device is (relative to traditional MOSFETs) and an understanding of its limitations,” said Mehrotra.

They were able to optimize a nanowire device design for both high performance and low operating power applications, thus advancing one of the technologies expected to help continue transistor scaling and extend Moore’s Law, according to which the number of transistors on a chip is expected to double about every two years.

- Anne Heavey, Open Science Grid

 This story also appeared as an OSG Research Highlight.

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