Europe's first 'green' exascale computer

An example of one of the ARM processors that will compose the new energy-efficient exascale computer. This level of computing represents a thousandfold increase over the current petascale machines. Image courtesy Renata Giménez Binder.

Energy efficiency is already a primary concern for the design of any computer system, and it is unanimously recognized that future exascale systems will be strongly constrained by their power consumption.

This is why the Mont-Blanc project, which was launched on 14th October in Barcelona with a kick-off meeting, has set the following objective: to design a new type of computer architecture capable of setting future global high-performance computing (HPC) standards that will deliver exascale performance while using 15 to 30 times less energy.

This new project is coordinated by the Barcelona Supercomputing Center (BSC), with a budget of over 14 million Euros, including over eight million Euros funded by the European Commission. Mont-Blanc has three objectives: first, to develop a fully functional energy efficient HPC prototype using low-power embedded technology; second, to design a next-generation HPC system together with a range of embedded technologies in order to overcome the limitations identified in the prototype system; third, to develop a portfolio of exascale applications to run on this new generation of HPC systems.

Increase in energy-efficiency

With energy efficiency being a key issue, high-performance computers are expected to achieve 200 petaflop/second in 2017 with a power budget of 10 megawatts (MW), and 1,000 petaflop/s (1 exaflop/s) in 2020, with a power budget of 20MW. That means an increase in energy-efficiency of more than 20 times compared with the most efficient supercomputers today.

“First, we must take into account that not all energy is used for computing within the cores. In current systems, the processors consume the lion’s share of the energy, often 40% or more. The remaining energy is used to power up the memory, interconnection network, and storage system. Furthermore, a significant fraction is wasted in power supply overheads, and in thermal dissipation (cooling), which do not contribute to performance at all,” says Alex Ramirez, leader of the Mont-Blanc project.

The system architecture in Mont-Blanc will rely on energy-efficient ARM processors, also used in embedded and mobile devices. It is expected to achieve an increase in energy-efficiency of up to four to 10 times compared with current technologies.

Alex Ramirez is leader of the Mont-Blanc project, an initiative that will carry Europe into the next phase of scientific challenges with a greener way of running e-infrastructures. Image courtesy Renata Giménez Binder.

The Mont-Blanc project will build on the experience of two previous ARM-based prototypes, developed under the PRACE prototyping efforts, an ARM multicore cluster built on Tegra2 dual-core Cortex-A9 chips, and an ARM+GPU cluster built from Tegra3 quad-core chips and mobile (MXM) GPU accelerators.

These prototypes will provide valuable feedback for the Mont-Blanc prototype, and will enable both application and system software development while the Mont-Blanc system is being developed.

The Mont-Blanc project brings on board: Bull, as the major HPC system vendor; ARM, as the world leader in embedded high-performance processors; and Gnodal, as interconnect partner that focuses its new product on scalability and power efficiency.

Besides the technology providers, Mont-Blanc unites the supercomputing centers from the four Tier-0 hosting partners in PRACE who have leading roles in system software and exascale application development: Germany (Forschungszentrum Jülich, BADW-LRZ), France (GENCI, CNRS), Italy (CINECA), and Spain (BSC).

They also run thousands of real applications, on a daily basis, on their Tier-0 and Tier-1 systems, from a vast number of scientific domains and serving a large community of academic and industrial users.

In order to assess the different hardware and software components made available during the project, an incremental approach will be used, working on both the porting and the optimization of small kernels, and then on real end-users’ scientific applications.

A version of this article was first published in the PRACE newsletter, Volume 6 – December 2011.